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Datasheet File OCR Text:

M29W128FH M29W128FL
128 Mbit (8Mb x 16 or 16Mb x 8, Page, Uniform Block) 3V Supply Flash Memory
Feature summary
Supply voltage - VCC = 2.7 to 3.6V for Program, Erase and Read - VPP =12V for Fast Program (optional) Asynchronous Random/Page Read - Page Width: 8 Words/16 Bytes - Page Access: 25, 30ns - Random Access: 60, 70ns Programming time - 10s per Byte/Word (typical) - 4 Words / 8 Bytes Program - 32-Word (64-Bytes) Write Buffer 64 KByte (32 KWord) Uniform Blocks Program/ Erase Suspend and Resume Modes - Read from any Block during Program Suspend - Read and Program another Block during Erase Suspend Unlock Bypass Program - Faster Production/Batch Programming Common Flash Interface - 64 bit Security Code 100,000 Program/Erase cycles per block Low power consumption - Standby and Automatic Standby Hardware Block Protection - VPP/WP pin for fast program and write protect of the highest (M29W128FH) or lowest block (M29W128FL) Extended Memory Block: Extra block used as security block or to store additional information
TSOP56 (N) 14 x 20mm
BGA

TBGA64 (ZA) 10 x 13mm Electronic Signature - Manufacturer Code: 0020h - Device Code: M29W128FH: 227Eh + 2212h + 228Ah M29W128FL: 227Eh + 2212h + 228Bh ECOPACK(R) packages

December 2007
Rev 7
1/78
www.numonyx.com
1
Contents
M29W128FH, M29W128FL
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Address Inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Input/Output or Address Input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . 12 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCC supply voltage (2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Vss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 3.2 3.3 3.4 3.5 3.6 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Special Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Verify Extended Memory Block Protection Indicator . . . . . . . . . . . . . . . 17 Verify Block Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Hardware Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Temporary Unprotect of high voltage Protected Blocks . . . . . . . . . . . . . 18
4
Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/78
M29W128FH, M29W128FL
Contents
4.2
Temporary Block Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 5.1.9 5.1.10 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2
Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 5.2.11 Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . 28 Write to Buffer and Program Confirm command . . . . . . . . . . . . . . . . . . 29 Write to Buffer and Program Abort and Reset command . . . . . . . . . . . 29 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3
Extended Memory Block Protection commands . . . . . . . . . . . . . . . . . . . 34
5.3.1 5.3.2 Enter Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . 34 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.0.1 6.0.2 6.0.3 6.0.4 6.0.5 6.0.6 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Write to Buffer and Program Abort Bit (DQ1) . . . . . . . . . . . . . . . . . . . . 38
3/78
Contents
M29W128FH, M29W128FL
7 8 9 10
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Appendix A Block addresses and Read/Modify Protection Groups . . . . . . . . . 54 Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
C.1 C.2 Factory Locked Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . 67 Customer Lockable Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . 68
Appendix D High Voltage Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
D.1 D.2 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Appendix E Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4/78
M29W128FH, M29W128FL
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus operations, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Electronic Signature, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block Protection, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bus operations, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Electronic Signature, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Protection, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Standard commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Standard commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Fast Program commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Fast Program commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Extended Block Protection commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Block Protection commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Program, Erase Times and Program, Erase Endurance cycles . . . . . . . . . . . . . . . . . . . . . 36 Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Write AC characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Write AC characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20mm, package mechanical data . . . 51 TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data. . . . . . . 52 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Block Addresses and Protection Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Extended Memory Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Programmer technique Bus operations, 8-bit or 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . 70 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5/78
List of figures
M29W128FH, M29W128FL
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Random Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Page Read AC waveforms (Word mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Write AC waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Write AC waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Reset/Block Temporary Unprotect AC waveforms (No Program/Erase ongoing) . . . . . . . 49 Reset/Block Temporary Unprotect during Program/Erase operation AC waveforms . . . . . 49 Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20mm, package outline . . . . . . . . . . . 51 TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline . . . . . . . . . . . . . . 52 Programmer equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Programmer equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 In-System equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 In-System equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Write to Buffer and Program flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . 75
6/78
M29W128FH, M29W128FL
Summary description
1
Summary description
The M29W128FH and M29W128FL are 128 Mbit (16Mb x8 or 8Mb x16) non-volatile memories that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. At Power-up the memories default to Read mode. The M29W128FH and M29W128FL are divided into 256 thirty-two KWord (sixty-four KByte) uniform blocks. Program and Erase commands are written to the Command Interface of the memory. An onchip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The Chip Enable, Output Enable and Write Enable signals control the bus operations of the memory. They allow simple connection to most microprocessors, often without additional logic. The devices support Asynchronous Random Read and Page Read from all blocks of the memory array. The M29W128FH and M29W128FL have an extra 128 Word (256 Byte) Extended Memory Block that can be accessed using a dedicated command. The Extended Memory Block can be protected and so is useful for storing security information. However the protection is irreversible, once protected the protection cannot be undone. Each block can be erased independently, so it is possible to preserve valid data while old data is erased. The devices feature two different levels of hardware block protection to avoid unwanted program or erase (modify):

The VPP/WP pin protects the highest block on the M29W128FH and the lowest block on the M29W128FL. The RP pin temporarily unprotects all the blocks previously protected using a High Voltage Block Protection technique (see Appendix D: High Voltage Block Protection).
The memories are offered in TSOP56 (14 x 20mm) and TBGA64 (10 x 13mm, 1mm pitch) packages. In order to meet environmental requirements, Numonyx offers the M29W128FH and the M29W128FL in ECOPACK(R) packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. The memories are supplied with all the bits erased (set to '1'). The M29W128FH and the M29W128FL will be referred to as M29W128F throughout the document. Table 1.
A0-A22
Signal names
Address Inputs
7/78
Summary description Table 1.
DQ0-DQ7 DQ8-DQ14 DQ15A- 1 E G W RP RB BYTE VCC VPP/WP VSS NC
M29W128FH, M29W128FL Signal names
Data Inputs/Outputs Data Inputs/Outputs Data Input/Output or Address Input Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Select Supply voltage VPP/Write Protect Ground Not Connected Internally
Figure 1.
Logic diagram
VCC VPP/WP
23 A0-A22 W E G RP BYTE M29W128FH M29W128FL
15 DQ0-DQ14 DQ15A-1
RB
VSS
AI11525
1. Also see Appendix A and Table 28 for a full listing of the Block Addresses.
8/78
M29W128FH, M29W128FL Figure 2. TSOP connections
Summary description
NC A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP A21 VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC
1
56
14 43 M29W128FH 15 M29W128FL 42
NC NC A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 NC VCC
AI11526
28
29
9/78
Summary description Figure 3. TBGA connections (top view through package)
1 2 3 4 5 6 7
M29W128FH, M29W128FL
8
A
NC
A3
A7
RB
W
A9
A13
NC
B
NC
A4
A17
VPP/WP
RP
A8
A12
A22
C
NC
A2
A6
A18
A21
A10
A14
NC
D
NC
A1
A5
A20
A19
A11
A15
VCC
E
NC
A0
DQ0
DQ2
DQ5
DQ7
A16
VSS
F
VCC
E
DQ8
DQ10
DQ12
DQ14
BYTE
NC
G
NC
G
DQ9
DQ11
VCC
DQ13
DQ15 A-1
NC
H
NC
VSS
DQ1
DQ3
DQ4
DQ6
VSS
NC
AI11527
10/78
M29W128FH, M29W128FL Figure 4. Block addresses
(x8) Address lines A22-A0, DQ15A-1 (x16) Address lines A22-A0
Summary description
FFFFFFh 64 KBytes FF0000h
7FFFFFh 32 KWords 7F8000h
Total of 256 Uniform Blocks
01FFFFh 64 KBytes 010000h 00FFFFh 64 KBytes 000000h
00FFFFh 32 KWords 008000h 007FFFh 32 KWords 000000h
AI11528
11/78
Signal descriptions
M29W128FH, M29W128FL
2
Signal descriptions
See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals connected to this device.
2.1
Address Inputs (A0-A22)
The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller.
2.2
Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.
2.3
Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.
2.4
Data Input/Output or Address Input (DQ15A- 1)
When the device is in x16 Bus mode, this pin behaves as a Data Input/Output pin (as DQ8DQ14). When the device is in x8 Bus mode, this pin behaves as an address pin; DQ15A- 1 Low will select the LSB of the addressed Word, DQ15A- High will select the MSB. 1 Throughout the text consider references to the Data Input/Output to include this pin when the device operates in x16 bus mode and references to the Address Inputs to include this pin when the device operates in x8 bus mode except when stated explicitly otherwise.
2.5
Chip Enable (E)
The Chip Enable pin, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored.
2.6
Output Enable (G)
The Output Enable pin, G, controls the Bus Read operation of the memory.
12/78
M29W128FH, M29W128FL
Signal descriptions
2.7
Write Enable (W)
The Write Enable pin, W, controls the Bus Write operation of the memory's Command Interface.
2.8
VPP/Write Protect (VPP/WP)
The VPP/Write Protect pin provides two functions. The VPP function allows the memory to use an external high voltage power supply to reduce the time required for Program operations. This is achieved by bypassing the unlock cycles and/or using the multiple Word (2 or 4 at-a-time) or multiple Byte Program (2, 4 or 8 at-a-time) commands. The Write Protect function provides a hardware method of protecting the highest or lowest block. When VPP/Write Protect is Low, VIL, the highest or lowest block is protected; Program and Erase operations on this block are ignored while VPP/Write Protect is Low, even when RP is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the highest or lowest block. Program and Erase operations can now modify the data in this block unless the block is protected using Block Protection. Applying VPPH to the VPP/WP pin will temporarily unprotect any block previously protected (including the highest or lowest block) using a High Voltage Block Protection technique (InSystem or Programmer technique). See Table 8: Hardware Protection for details. When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP (see Figure 15: Accelerated Program Timing waveforms). Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. The VPP/Write Protect pin must not be left floating or unconnected or the device may become unreliable. A 0.1F capacitor should be connected between the VPP/Write Protect pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, IPP.
13/78
Signal descriptions
M29W128FH, M29W128FL
2.9
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all the blocks previously protected using a High Voltage Block Protection technique (In-System or Programmer technique). Note that if VPP/WP is at VIL, then the highest or lowest block will remain protected even if RP is at VID. A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See Section 2.10: Ready/Busy Output (RB), Table 24: Reset/Block Temporary Unprotect AC characteristics and Figure 13 and Figure 14 for more details. Holding RP at VID will temporarily unprotect all the blocks previously protected using a High Voltage Block Protection technique. Program and erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH.
2.10
Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or erase operation. During Program or erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 24: Reset/Block Temporary Unprotect AC characteristics and Figure 13 and Figure 14. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.
2.11
Byte/Word Organization Select (BYTE)
It is used to switch between the x8 and x16 Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in x8 mode, when it is High, VIH, the memory is in x16 mode.
2.12
VCC supply voltage (2.7V to 3.6V)
VCC provides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1F capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, Icc2.
14/78
M29W128FH, M29W128FL
Signal descriptions
2.13
Vss ground
VSS is the reference for all voltage measurements. The device features two VSS pins both of which must be connected to the system ground.
15/78
Bus operations
M29W128FH, M29W128FL
3
Bus operations
There are five standard bus operations that control the device. These are Bus Read (Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby. See Table 2 and Table 5, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable, Write Enable, and Reset/Block Temporary Unprotect pins are ignored by the memory and do not affect bus operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command Interface. To speed up the read operation the memory array can be read in Page mode where data is internally read and stored in a page buffer. The Page has a size of 8 Words (or 16 Bytes) and is addressed by the address inputs A2-A0 in x16 mode and A2-DQ15A- in 1 Byte mode. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 9: Random Read AC waveforms, Figure 10: Page Read AC waveforms (Word mode), and Table 21: Read AC characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figure 11 and Figure 12, Write AC Waveforms, and Table 22 and Table 23, Write AC Characteristics, for details of the timing requirements.
3.3
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4
Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC 0.3V. For the Standby current level see Table 20: DC characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes.
16/78
M29W128FH, M29W128FL
Bus operations
3.5
Automatic Standby
If CMOS levels (VCC 0.3V) are used to drive the bus and the bus is inactive for tAVQV+ 30ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.
3.6
Special Bus operations
Additional bus operations can be performed to read the Electronic Signature, verify the Protection Status of the Extended Memory Block, and apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.
3.6.1
Read Electronic Signature
The memory has two codes, the Manufacturer code and the Device code used to identify the memory. These codes can accessed by performing read operations with control signals and addresses set as shown in Table 3 and Table 5. These codes can also be accessed by issuing an Auto Select command (see Section 5.1.2: Auto Select command).
3.6.2
Verify Extended Memory Block Protection Indicator
The Extended Memory Block is either Factory Locked or Customer Lockable. The Protection Status of the Extended Memory Block (Factory Locked or Customer Lockable) can be accessed by reading the Extended Memory Block Protection Indicator. This is performed by applying the signals as shown in Table 4 and Table 7. The Protection Status of the Extended Memory Block is then output on bit DQ7 of the Data Input/Outputs. (see Table 2 and Table 5, Bus Operations). The Protection Status of the Extended Memory Block can also be accessed by issuing an Auto Select command (see Section 5.1.2: Auto Select command).
3.6.3
Verify Block Protection Status
The Protection Status of a Block can be directly accessed by performing a read operation with control signals and addresses set as shown in Table 4 and Table 7. If the Block is protected, then 01h (in x8 mode) is output on Data Input/Outputs DQ0-DQ7, otherwise 00h is output.
3.6.4
Hardware Block Protect
The VPP/WP pin can be used to protect the highest or lowest block. When VPP/WP is at VIL the highest or lowest block is protected and remains protected regardless of the Block Protection Status or the Reset/Block Temporary Unprotect pin state.
17/78
Bus operations
M29W128FH, M29W128FL
3.6.5
Temporary Unprotect of high voltage Protected Blocks
The RP pin can be used to temporarily unprotect all the blocks previously protected using the In-System or the Programmer protection technique (High Voltage techniques). Refer to Section 2.9: Reset/Block Temporary Unprotect (RP). Table 2. Bus operations, 8-bit mode
Address Inputs E VIL VIL X VIH G VIL VIH VIH X W VIH VIL VIH X RP VIH VIH VIH VIH VPP/WP A22-A0, DQ15A-1 Bus Read Bus Write Output Disable Standby
1. X = VIL or VIH.
Operation(1)
Data Inputs/Outputs DQ14-DQ8 Hi-Z Hi-Z Hi-Z Hi-Z DQ7-DQ0 Data Output Data Input Hi-Z Hi-Z
VIH VIH VIH VIH
Cell Address Command Address X X
Table 3.
Read Cycle(1) Manufacturer Code Device Code (Cycle 1) Device Code (Cycle 2) Device Code (Cycle 3)
Read Electronic Signature, 8-bit mode
Address Inputs EGW A22-A10 A9 A8-A7 A6 A5-A4 A3 A2 A1 A0 DQ15A-1 VIL VIL VIL VIL VIL VIL VIL VIH VIL VIL VIH X VID X VIL X VIH VIH VIH VIL VIH VIH VIH VIH X X Hi-Z 12h (Both Devices) Hi-Z 8Ah (M29W128FH) 8Bh (M29W128FL) X X Data Inputs/Outputs DQ14DQ8 Hi-Z DQ7-DQ0 20h
Hi-Z 7Eh (Both Devices)
1. X = VIL or VIH.
18/78
M29W128FH, M29W128FL Table 4.
Operation
(1)
Bus operations
Block Protection, 8-bit mode
E G Address Inputs Data Inputs/Outputs VPP/ W RP A8A5- A3DQ15 DQ14 WP A22- A11A9 A6 A1 A0 DQ7-DQ0 A12 A10 A7 A4 A2 A-1 -DQ8 M29W128FH 88h (factory locked) 08h (customer lockable) M29W128FL 98h (factory locked) 18h (customer lockable) 01h (protected) 00h (unprotected)
Verify Extended Memory Block Protection Indicator (bit DQ7)
VIH VIL VIL VIH VIH VIH BA X VID X VIL X VIL VIH X Hi-Z
Verify Block Protection Status Temporary Block Unprotect
(2)
VIL
X
X
X VID
X
Valid
Data Input
1. X = VIL or VIH. BA any Address in the Block. 2. The RP pin unprotects all the blocks that have been previously protected using a High Voltage protection Technique.
Table 5.
Bus operations, 16-bit mode
E VIL VIL X VIH G VIL VIH W VIH VIL RP VIH VIH VIH VIH VPP/ WP VIH VIH VIH VIH Address Inputs A22-A0 Cell Address Command Address X X Data Inputs/Outputs DQ15A-1, DQ14-DQ0 Data Output Data Input Hi-Z Hi-Z
Operation(1) Bus Read Bus Write Output Disable Standby
1. X = VIL or VIH.
VIH VIH X X
19/78
Bus operations Table 6.
Read Cycle
M29W128FH, M29W128FL
Read Electronic Signature, 16-bit mode
Address Inputs
(1)
Data Inputs/Outputs A2 VIL VIL VIH VIH A1 VIL VIL VIH VIH A0 VIL VIH VIL VIH DQ15A-1, DQ14-DQ0 0020h 227Eh (Both Devices) 2212h (Both Devices) 228Ah (M29W128FH) 228Bh (M29W128FL)
E
G
W
A22A8A9 A10 A7
A6
A5A4
A3 VIL VIL
Manufacturer Code Device Code (Cycle 1) Device Code (Cycle 2) Device Code (Cycle 3)
1. X = VIL or VIH.
VIL VIL VIH
X
VID
X
VIL
X VIH VIH
Table 7.
Block Protection, 16-bit mode
Address Inputs VPP/ RP A8A5- A3WP A22- A11A9 A6 A1 A0 A12 A10 A7 A4 A2 Data Inputs/Outputs DQ15A-1, DQ14-DQ0 M29W128FH 0088h (factory locked) 0008h (customer lockable) VIH BA X VID X VIL X VIL VIH M29W128FL 0098h (factory locked) 0018h (customer lockable) 0001h (protected) 0000h (unprotected)
Operation(1)
E
G
W
Verify Extended Memory Block Indicator VIL VIL VIH VIH VIH (bit DQ7)
Verify Block Protection Status Temporary Block Unprotect (2) X X X VID X Valid
VIL
Data Input
1. X = VIL or VIH. BA Any Address in the Block. 2. The RP pin unprotects all the blocks that have been previously protected using a High Voltage protection Technique.
20/78
M29W128FH, M29W128FL
Hardware protection
4
Hardware protection
The M29W128F features hardware protection/unprotection. Refer to Table 8 for details on hardware block protection/unprotection using VPP/WP and RP pins.
4.1
Write Protect
The VPP/WP pin protects the highest or lowest block (refer to Section 2: Signal descriptions for a detailed description of the signals).
4.2
Temporary Block Unprotect
When held at VID, the Reset/Block Temporary Unprotect pin, RP, will temporarily unprotect all the blocks previously protected using a High Voltage Block Protection technique. Table 8.
VPP/WP
Hardware Protection
RP VIH Function Highest or lowest block protected from Program/Erase operations All blocks temporarily unprotected except the highest or lowest block All blocks temporarily unprotected All blocks temporarily unprotected
VIL VID VIH or VID VPPH VID VIH or VID
21/78
Command interface
M29W128FH, M29W128FL
5
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode.
5.1
Standard commands
See either Table 9, or Table 10, depending on the configuration that is being used, for a summary of the Standard commands.
5.1.1
Read/Reset command
The Read/Reset command returns the memory to Read mode. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to Read mode. If the Read/Reset command is issued during the time-out of a Block erase operation, the memory will take up to 10s to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend.
5.1.2
Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code, the Protection Status of each block (Block Protection Status) and the Extended Memory Block Protection Indicator. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued Bus Read operations to specific addresses output the Manufacturer Code, the Device Code, the Extended Memory Block Protection Indicator and a Block Protection Status (see Table 9 and Table 10 in conjunction with Table 3, Table 4, Table 6 and Table 7). The memory remains in Auto Select mode until a Read/Reset or CFI Query command is issued.
5.1.3
Read CFI Query command
The Read CFI Query Command is used to put the memory in Read CFI Query mode. Once in Read CFI Query mode, Bus Read operations to the memory will output data from the Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the Read CFI Query Command. This command is valid only when the device is in the Read Array or Auto Select mode. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Auto Select mode). A second Read/Reset command is required to put the device in Read Array mode from Auto Select mode.
22/78
M29W128FH, M29W128FL
Command interface
See Appendix B, Table 29, Table 30, Table 31, Table 32, Table 33 and Table 34 for details on the information contained in the Common Flash Interface (CFI) memory area.
5.1.4
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected, then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 15. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to '1'. All previous data is lost.
5.1.5
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. It sets all of the bits in the unprotected selected blocks to '1'. All previous data in the selected blocks is lost. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller after a time-out period of 50s after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50s of the last block. The 50s timer restarts when an additional block is selected. After the sixth Bus Write operation, a Bus Read operation outputs the Status Register. See Section 6: Status register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. After the Block Erase operation has completed, the memory returns to the Read mode, unless an error has occurred. When an error occurs, Bus Read operations will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command and the Read/Reset command which is only accepted during the 50s time-out period. Typical block erase times are given in Table 15.
23/78
Command interface
M29W128FH, M29W128FL
5.1.6
Erase Suspend command
The Erase Suspend command may be used to temporarily suspend a Block or multiple Block Erase operation. One Bus Write operation is required to issue the command. Issuing the Erase Suspend command returns the whole device to Read mode. The Program/Erase Controller will suspend within the Erase Suspend Latency time (see Table 15: Program, Erase Times and Program, Erase Endurance cycles) of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. During Erase Suspend a Bus Read operation to the Extended Memory Block will output the Extended Memory Block data. Once in the Extended Block mode, the Exit Extended Block command must be issued before the erase operation can be resumed.
5.1.7
Erase Resume command
The Erase Resume command is used to restart the Program/Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An Erase can be suspended and resumed more than once.
5.1.8
Program Suspend command
The Program Suspend command allows the system to interrupt a program operation so that data can be read from any block. When the Program Suspend command is issued during a program operation, the device suspends the program operation within the Program Suspend Latency time (see Table 15: Program, Erase Times and Program, Erase Endurance cycles) and updates the Status Register bits. After the program operation has been suspended, the system can read array data from any address. However, data read from Program-Suspended addresses is not valid. The Program Suspend command may also be issued during a program operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Extended Memory Block area (One-time Program area), the user must use the proper command sequences to enter and exit this region. The system may also issue the Auto Select command sequence when the device is in the Program Suspend mode. The system can read as many Auto Select codes as required.
24/78
M29W128FH, M29W128FL
Command interface
When the device exits the Auto Select mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Auto Select command sequence for more information.
5.1.9
Program Resume command
After the Program Resume command is issued, the device reverts to programming. The controller can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Refer to Section 6: Status register for details. The system must issue a Program Resume command, to exit the Program Suspend mode and to continue the programming operation. Further issuing of the Resume command is ignored. Another Program Suspend command can be written after the device has resumed programming.
5.1.10
Program command
The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final Write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. Programming can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 5.1.8: Program Suspend command and Section 5.1.9: Program Resume command). If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. After programming has started, Bus Read operations output the Status Register content. See Section 6: Status register for more details. Typical program times are given in Table 15: Program, Erase Times and Program, Erase Endurance cycles. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs, Bus Read operations to the memory continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'.
25/78
Command interface Table 9. Standard commands, 8-bit mode
M29W128FH, M29W128FL
Bus operations(1)(2) Command Length 1st Add 1 Read/Reset 3 Manufacturer Code Device Code Auto Select Extended Memory Block Protection Indicator Block Protection Status Program Chip Erase Block Erase Erase/Program Suspend Erase/Program Resume Read CFI Query 4 6 6 + 1 1 1 AAA AAA AAA X X AA AA AA AA B0 30 98 555 555 555 55 55 55 AAA AAA AAA A0 80 80 PA AAA AAA PD AA AA 555 555 55 55 AAA BA 10 30 3 AAA AA 555 55 AAA 90
(3) (3)
2nd Data Add Data F0 AA 555 55 X
3rd Add
4th
5th
6th
Data Add Data Add Data Add Data
X AAA
F0
1. Grey cells represent Read cycles. The other cells are Write cycles. 2. X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. 3. The Auto Select addresses and data are given in Table 3: Read Electronic Signature, 8-bit mode, and Table 4: Block Protection, 8-bit mode, except for A9 that is `Don't Care'.
26/78
M29W128FH, M29W128FL Table 10. Standard commands, 16-bit mode
Bus operations(1)(2) Command Length 1st Add 1 Read/Reset 3 Manufacturer Code Device Code Extended Memory Auto Select Block Protection Indicator Block Protection Status Program Chip Erase Block Erase Erase/Program Suspend Erase/Program Resume Read CFI Query 4 6 6+ 1 1 1 555 555 555 X X 55 AA AA AA B0 30 98 2AA 2AA 2AA 55 55 55 555 555 555 A0 80 80 PA 555 555 PD AA AA 3 555 AA 2AA 55 555 90
(3) (3)
Command interface
2nd Data Add Data F0 AA 2AA 55 X
3rd Add
4th
5th
6th
Data Add Data Add Data Add Data
X 555
F0
2AA 2AA
55 55
555 BA
10 30
1. Gray cells represent Read cycles. The other cells are Write cycles. 2. X Don't Care, PA Program Address, PD Program Data, BA any address in the Block. All values in the table are in hexadecimal. 3. The Auto Select addresses and data are given in Table 6: Read Electronic Signature, 16-bit mode, and Table 7: Block Protection, 16-bit mode, except for A9 that is `Don't Care'.
27/78
Command interface
M29W128FH, M29W128FL
5.2
Fast Program commands
The M29W128F offers a set of Fast Program commands to improve the programming throughput:

Write to Buffer and Program Double and Quadruple Word, Program Double, Quadruple and Octuple Byte Program Unlock Bypass.
See either Table 12, or Table 11, depending on the configuration that is being used, for a summary of the Fast Program commands. When VPPH is applied to the VPP/Write Protect pin the memory automatically enters the Fast Program mode. The user can then choose to issue any of the Fast Program commands. Care must be taken because applying a VPPH to the VPP/WP pin will temporarily unprotect any protected block. After programming has started, Bus Read operations in the memory output the Status Register content. Fast program commands can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 5.1.8: Program Suspend command and Section 5.1.9: Program Resume command) After the fast program operation has completed, the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Typical Program times are given in Table 15: Program, Erase Times and Program, Erase Endurance cycles.
5.2.1
Write to Buffer and Program command
The Write to Buffer and Program Command makes use of the device's 64-Byte Write Buffer to speed up programming. 32 Words/64 Bytes can be loaded into the Write Buffer. Each Write Buffer has the same A22-A5 addresses.The Write to Buffer and Program command dramatically reduces system programming time compared to the standard non-buffered Program command. When issuing a Write to Buffer and Program command, the VPP/WP pin can be either held High, VIH or raised to VPPH. See Table 15 for details on typical Write to Buffer and Program times in both cases. Five successive steps are required to issue the Write to Buffer and Program command: 1. 2. 3. The Write to Buffer and Program command starts with two unlock cycles. The third Bus Write cycle sets up the Write to Buffer and Program command. The setup code can be addressed to any location within the targeted block. The fourth Bus Write cycle sets up the number of Words/Bytes to be programmed. Value N is written to the same block address, where N+1 is the number of Words/Bytes to be programmed. N+1 must not exceed the size of the Write Buffer or the operation will abort. The fifth cycle loads the first address and data to be programmed.
4.
28/78
M29W128FH, M29W128FL
Command interface
Use N Bus Write cycles to load the address and data for each Word/Byte into the Write Buffer. Addresses must lie within the range from the start address+1 to the start address + N-1. Optimum performance is obtained when the start address corresponds to a 64 Byte boundary. If the start address is not aligned to a 64 Byte boundary, the total programming time is doubled. All the addresses used in the Write to Buffer and Program operation must lie within the same page. To program the content of the Write Buffer, this command must be followed by a Write to Buffer and Program Confirm command. If an address is written several times during a Write to Buffer and Program operation, the address/data counter will be decremented at each data load operation and the data will be programmed to the last word loaded into the Buffer. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will abort the Write to Buffer and Program. The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during a Write to Buffer and Program operation. If is not possible to detect Program operation fails when changing programmed data from `0' to `1', that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous value and the current value. A Write to Buffer and Program Abort and Reset command must be issued to abort the Write to Buffer and Program operation and reset the device in Read mode. See Appendix E, Figure 22: Write to Buffer and Program flowchart and Pseudo Code, for a suggested flowchart on using the Write to Buffer and Program command.
5.2.2
Write to Buffer and Program Confirm command
The Write to Buffer and Program Confirm command is used to confirm a Write to Buffer and Program command and to program the N+1 Words/Bytes loaded in the Write Buffer by this command.
5.2.3
Write to Buffer and Program Abort and Reset command
The Write to Buffer and Program Abort and Reset command is used to abort Write to Buffer and Program command.
5.2.4
Double Word Program command
This is used to write two adjacent Words in x16 mode, simultaneously. The addresses of the two Words must differ only in A0. Three bus write cycles are necessary to issue the command: 1. 2. 3. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first Word to be written. The third bus cycle latches the Address and the Data of the second Word to be written and starts the Program/Erase Controller.
29/78
Command interface
M29W128FH, M29W128FL
5.2.5
Quadruple Word Program command
This is used to write a page of four adjacent Words (or 8 adjacent Bytes), in x16 mode, simultaneously. The addresses of the four Words must differ only in A1 and A0. Five bus write cycles are necessary to issue the command: 1. 2. 3. 4. 5. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first Word to be written. The third bus cycle latches the Address and the Data of the second Word to be written. The fourth bus cycle latches the Address and the Data of the third Word to be written. The fifth bus cycle latches the Address and the Data of the fourth Word to be written and starts the Program/Erase Controller.
5.2.6
Double Byte Program command
This is used to write two adjacent Bytes in x8 mode, simultaneously. The addresses of the two Bytes must differ only in DQ15A-1. Three bus write cycles are necessary to issue the command: 6. 7. 8. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first Byte to be written. The third bus cycle latches the Address and the Data of the second Byte to be written and starts the Program/Erase Controller.
5.2.7
Quadruple Byte Program command
This is used to write four adjacent Bytes in x8 mode, simultaneously. The addresses of the four Bytes must differ only in A0, DQ15A-1. Five bus write cycles are necessary to issue the command. 1. 2. 3. 4. 5. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first Byte to be written. The third bus cycle latches the Address and the Data of the second Byte to be written. The fourth bus cycle latches the Address and the Data of the third Byte to be written. The fifth bus cycle latches the Address and the Data of the fourth Byte to be written and starts the Program/Erase Controller.
30/78
M29W128FH, M29W128FL
Command interface
5.2.8
Octuple Byte Program command
This is used to write eight adjacent Bytes, in x8 mode, simultaneously. The addresses of the eight Bytes must differ only in A1, A0 and DQ15A-1. Nine bus write cycles are necessary to issue the command: 1. 2. 3. 4. 5. 6. 7. 8. 9. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first Byte to be written. The third bus cycle latches the Address and the Data of the second Byte to be written. The fourth bus cycle latches the Address and the Data of the third Byte to be written. The fifth bus cycle latches the Address and the Data of the fourth Byte to be written. The sixth bus cycle latches the Address and the Data of the fifth Byte to be written. The seventh bus cycle latches the Address and the Data of the sixth Byte to be written. The eighth bus cycle latches the Address and the Data of the seventh Byte to be written. The ninth bus cycle latches the Address and the Data of the eighth Byte to be written and starts the Program/Erase Controller.
5.2.9
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued, the memory enters Unlock Bypass mode. When in Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. The Unlock Bypass Program command can then be issued to program addresses within the memory, or the Unlock Bypass Reset command can be issued to return the memory to Read mode. In Unlock Bypass mode the memory can be read as if in Read mode.
5.2.10
Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. The operation cannot be aborted, a Bus Read operation to the memory outputs the Status Register. See the Program command for details on the behavior.
5.2.11
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass mode.
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Command interface Table 11. Fast Program commands, 8-bit mode
Bus Write operations(1) Command Length 1st Add Write to Buffer and Program Write to Buffer and Program Abort and Reset Write to Buffer and Program Confirm Double Byte Program Quadruple Byte Program Octuple Byte Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset 1. 2. 3. 4. 5. N +5 Data 2nd Add Data 3rd Add Data 4th Add Data N(2) 5th Add PA(3) Data 6th Add WBL
(4)
M29W128FH, M29W128FL
7th Add Data
8th Add Data
9th Add Data
Data
AAA
AA
555
55
BA
25
BA
PD
PD
3
AAA
AA
555
55
AAA
F0
1
BA(5)
29
3
AAA
50
PA0
PD0
PA1
PD1
5
AAA
56
PA0
PD0
PA1
PD1
PA2
PD2
PA3
PD3
9
AAA
8B
PA0
PD0
PA1
PD1
PA2
PD2
PA3
PD3
PA4
PD4
PA5
PD5
PA6
PD6
PA7
PD7
3
AAA
AA
555
55
AAA
20
2
X
A0
PA
PD
2
X
90
X
00
X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block, WBL Write Buffer Location. All values in the table are in hexadecimal. The maximum number of cycles in the command sequence is 68. N+1 is the number of Bytes to be programmed during the Write to Buffer and Program operation. Each buffer has the same A22-A5 addresses. A0-A4 and A-1 are used to select a Byte within the N+1 Byte page. The 6th cycle has to be issued N time. WBL scans the Word inside the page. BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles.
32/78
M29W128FH, M29W128FL Table 12. Fast Program commands, 16-bit mode
Bus Write operations(1) Command Length 1st Add Write to Buffer and Program Write to Buffer and Program Abort and Reset Write to Buffer and Program Confirm Double Word Program Quadruple Word Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset N+ 5 3 1 3 5 3 2 2 555 555 BA(5) 555 555 555 X X Data AA AA 29 50 56 AA A0 90 PA0 PA0 2AA PA X PD0 PD0 55 PD 00 PA1 PA1 555 PD1 PD1 20 PA2 PD2 2nd Add 2AA 2AA Data 55 55 Add BA 555 3rd Data 25 F0 Add BA 4th Data N(2)
Command interface
5th Add PA(3) Data PD
6th Add WBL
(4)
Data PD
PA3
PD3
1. X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block, WBL Write Buffer Location. All values in the table are in hexadecimal. 2. The maximum number of cycles in the command sequence is 36. N+1 is the number of Words to be programmed during the Write to Buffer and Program operation. 3. Each buffer has the same A22-A5 addresses. A0-A4 are used to select a Word within the N+1 Word page. 4. The 6th cycle has to be issued N time. WBL scans the Word inside the page. 5. BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles.
33/78
Command interface
M29W128FH, M29W128FL
5.3
Extended Memory Block Protection commands
The M29W128F offers a set of commands to access the Extended Memory Block and to configure and check its protection mode. The commands related to the Extended Memory Block Protection are available in both 8 bit and 16 bit memory configuration.
5.3.1
Enter Extended Memory Block command
The M29W128F has one extra 128 Word block (Extended Memory Block) that can only be accessed using the Enter Extended Memory Block command. Three Bus Write cycles are required to issue the Extended Memory Block command. Once the command has been issued the device enters the Extended Memory Block mode where all Bus Read or Program operations are conducted on the Extended Memory Block. Once the device is in the Extended Block mode, the Extended Memory Block is addressed by using the addresses occupied by block 0 in the other operating modes (see Table 28: Block Addresses and Protection Groups). The device remains in Extended Block mode until the Exit Extended Block command is issued or power is removed from the device. After power-up or a hardware reset, the device reverts to the Read mode where commands issued to block 0 address space will address block 0. Note that when the device is in the Extended Block mode, the VPP/WP pin cannot be used for fast programming and the Unlock Bypass mode is not available. The Extended Memory Block cannot be erased, and can be treated as one-time programmable (OTP) memory. In Extended Block mode, Erase, Chip Erase, Erase Suspend and Erase resume commands are not allowed. To exit from the Extended Block mode the Exit Extended Block command must be issued. The Extended Memory Block can be protected by setting the Extended Memory Block Protection Bit to `1'; however once protected the protection cannot be undone.
5.3.2
Exit Extended Block command
The Exit Extended Block command is used to exit from the Extended Block mode and return the device to Read mode. Four Bus Write operations are required to issue the command.
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M29W128FH, M29W128FL Table 13. Extended Block Protection commands, 8-bit mode
Bus operations(1)(2) Command Length 1st 2nd 3rd Add AAA AAA 4th
Command interface
5th
6th
Add Data Add Data Enter Extended Block Exit Extended Block 3 4 AAA AAA AA AA 555 555 55 55
Data Add Data Add 88 90 X 00
Data Add Data
1. X Don't Care. All values in the table are in hexadecimal. 2. Grey cells represent Read cycles. The other cells are Write cycles.
Table 14.
Block Protection commands, 16-bit mode
Bus operations(1)(2)(3) Length
Command
1st
2nd
3rd
4th Add
5th
6th
7th
Add Data Add Data Add Data Enter Extended Block 3 555 555 AA AA 2AA 2AA 55 55 555 555 88 90
Data Add Data Add
Data Add Data
Exit Extended Block 4
X
00
1. Grey cells represent Read cycles. The other cells are Write cycles. 2. X Don't Care. All values in the table are in hexadecimal. 3. During Command cycles, if the lower address bits are 555h or 2AAh then the address bits higher than A11 and data bits higher than DQ7 are Don't Care.
35/78
Command interface Table 15.
M29W128FH, M29W128FL
Program, Erase Times and Program, Erase Endurance cycles
Parameter Min Typ (1)(2) 80 0.8 Max(2) 400(3) 6
(4)
Unit s s s s
Chip Erase Block Erase (64 KBytes) Erase Suspend Latency Time Single or Multiple Byte Program (1, 2, 4 or 8 Bytes at-a-time) Byte Program Write to Buffer and Program (64 Bytes at-a-time) VPP/WP =VPPH VPP/WP=VIH
50(4) 10 90 280 10 90 280 80 40 20 10 5 100,000 20 400(3) 200(3) 100(3) 50(3) 15 200(3) 200(3)
s
Single or Multiple Word Program (1, 2 or 4 Words at-a-time) Word Program Write to Buffer and Program (32 Words at-a-time) Chip Program (Byte by Byte) Chip Program (Word by Word) Chip Program (Quadruple Byte or Double Word) Chip Program (Octuple Byte or Quadruple Word) Program Suspend Latency Time Program/Erase Cycles (per Block) Data Retention
1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested.
s
VPP/WP= VPPH VPP/WP=VIH
s
s s s s s cycles years
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. 4. Maximum value measured at worst case conditions for both temperature and VCC.
36/78
M29W128FH, M29W128FL
Status register
6
Status register
The M29W128F has one Status Register. The Status Register provides information on the current or previous Program or Erase operations. The various bits convey information and errors on the operation. Bus Read operations from any address within the memory, always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 16: Status register bits.
6.0.1
Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read mode. In Erase Suspend mode the Data Polling Bit will output a '1' during a Bus Read operation within a block being erased. The Data Polling Bit will change from a '0' to a '1' when the Program/Erase Controller has suspended the Erase operation.
Figure 5: Data Polling flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased.
6.0.2
Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During a Program/Erase operation the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation.
Figure 6: Toggle flowchart, gives an example of how to use the Data Toggle Bit.
37/78
Status register
M29W128FH, M29W128FL
6.0.3
Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to '1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to '0' back to '1' and attempting to do so will set DQ5 to `1'. A Bus Read operation to that address will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'.
6.0.4
Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to '1'. Before the Program/Erase Controller starts the Erase Timer Bit is set to '0' and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read.
6.0.5
Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory array data as if in Read mode. After an Erase operation that causes the Error Bit to be set, the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly.
6.0.6
Write to Buffer and Program Abort Bit (DQ1)
The Write to Buffer and Program Abort bit, DQ1, is set to `1' when a Write to Buffer and Program operation aborts. The Write to Buffer and Program Abort and Reset command must be issued to return the device to Read mode (see Write to Buffer and Program in COMMANDS section).
38/78
M29W128FH, M29W128FL Table 16. Status register bits(1)
Operation Program Program During Erase Suspend Write to Buffer and Program Abort Program Error Chip Erase Block Erase before timeout 0 0 Block Erase 0 1 Erase Suspend Data read as normal 0 Erase Error 0
1. Unspecified data bits should be ignored.
Status register
DQ7 DQ7 DQ7 DQ7 DQ7 0 0
DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle
DQ5 0 0 0 1 0 0 0 0 0 0
DQ3 - - - - 1 0 0 1 1 -
DQ2 - - - - Toggle Toggle No Toggle Toggle No Toggle Toggle
DQ1 0 - 1 - - - - - - - -
RB 0 0 0 Hi-Z 0 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z
Toggle Toggle
1 1
1 1
No Toggle Toggle
- -
Figure 5.
Data Polling flowchart
START
READ DQ5 & DQ7 at VALID ADDRESS
DQ7 = DATA NO NO DQ5 = 1 YES
YES
READ DQ7 at VALID ADDRESS
DQ7 = DATA NO FAIL
YES
PASS
AI07760
39/78
Status register Figure 6. Toggle flowchart
START READ DQ6 at Valid Address READ DQ5 & DQ6 at Valid Address
M29W128FH, M29W128FL
DQ6 = TOGGLE YES NO DQ5 =1 YES
NO
READ DQ6 TWICE at Valid Address
DQ6 = TOGGLE YES FAIL
NO
PASS
AI11530
40/78
M29W128FH, M29W128FL
Maximum rating
7
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 17.
Symbol TBIAS TSTG VIO VCC VID VPP(3)
Absolute maximum ratings
Parameter Temperature Under Bias Storage Temperature Input or Output Supply voltage Identification voltage Program voltage voltage(1)(2) Min - 50 -65 -0.6 -0.6 -0.6 -0.6 Max 125 150 VCC + 0.6 4 13.5 13.5 Unit C C V V V V
1. Minimum voltage may undershoot to - during transition and for less than 20ns during transitions. 2V 2. Maximum voltage may overshoot to VCC + 2V during transition and for less than 20ns during transitions. 3. VPP must not remain at 12V for more than a total of 80hrs.
41/78
DC and AC parameters
M29W128FH, M29W128FL
8
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 18: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 18. Operating and AC measurement conditions
M29W128FH, M29W128FL Parameter Min VCC supply voltage Ambient Operating Temperature Load capacitance (CL) Input Rise and Fall Times Input pulse voltages Input and Output Timing Ref. voltages 0 to VCC VCC/2 2.7 -40 30 10 0 to VCC VCC/2 60 Max 3.6 85 Min 2.7 -40 30 10 70 Max 3.6 85 V C pF ns V V Unit
Figure 7.
AC measurement load circuit
VPP VCC VCC
25k DEVICE UNDER TEST 25k
CL 0.1F 0.1F
CL includes JIG capacitance
AI05558
42/78
2 9 1 2 8 , 2 9 1 2 8
DC and AC parameters
Figure 8.
AC measurement I/O waveform
VCC VCC/2 0V
AI05557
Table 19.
Symbol CIN COUT
Device capacitance(1)
Parameter Input Capacitance Output Capacitance Test condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
1. Sampled only, not 100% tested.
Table 20.
Symbol ILI ILO ICC1 ICC2
DC characteristics
Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) Test condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIH, f = 6MHz E = VCC 0.2V, RP = VCC 0.2V Program/Erase Controller active VPP/WP = VIL or VIH VPP/WP = VPPH -0.5 0.7VCC VCC = 2.7V 10% VCC = 2.7V 10% IOL = 1.8mA IOH = -100A VCC -0.4 11.5 1.8 12.5 2.3 11.5 Min Max 1 1 10 100 20 20 0.8 VCC + 0.3 12.5 15 0.45 Unit
A A
mA
A
mA mA V V V mA V V V V
ICC3 (1)
Supply Current (Program/Erase)
VIL VIH VPPH IPP VOL VOH VID VLKO
Input Low voltage Input High voltage Voltage for VPP/WP Program Acceleration Current for VPP/WP Program Acceleration Output Low voltage Output High voltage Identification voltage Program/Erase Lockout Supply voltage
1. Sampled only, not 100% tested.
43/78
DC and AC parameters Figure 9. Random Read AC waveforms
M29W128FH, M29W128FL
tAVAV A0-A22/ A-1 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ7/ DQ8-DQ15 tBHQV BYTE tELBL/tELBH tBLQZ
AI08970
VALID tAXQX
tEHQX tEHQZ
tGHQX tGHQZ VALID
44/78
M29W128FH, M29W128FL
A3-A22 A-1 VALID
A0-A2 VALID VALID VALID VALID VALID VALID VALID
VALID
tAVQV
E tEHQX tEHQZ
Figure 10. Page Read AC waveforms (Word mode)
tELQV
G tGLQV tAVQV1 VALID VALID VALID VALID VALID VALID VALID tGHQX tGHQZ VALID
DQ0-DQ15
AI08971c
DC and AC parameters
45/78
DC and AC parameters Table 21.
Symbol
M29W128FH, M29W128FL
Read AC characteristics
Alt Parameter Test condition M29W128FH, M29W128FL 60 70 70 70 30 0 70 0 25 25 25 0 ns ns ns ns ns ns ns ns ns ns Unit
tAVAV tAVQV tAVQV1 tELQX(1) tELQV tGLQX(1) tGLQV tEHQZ(1) tGHQZ(1) tEHQX tGHQX tAXQX tELBL tELBH tBLQZ tBHQV
tRC tACC
Address Valid to Next Address Valid Address Valid to Output Valid
E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL
Min Max Max Min Max Min Max Max Max Min
60 60 25 0 60 0 20 25 25 0
tPAGE Address Valid to Output Valid (Page) tLZ tCE tOLZ tOE tHZ tDF tOH Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition
tELFL Chip Enable to BYTE Low or High tELFH tFLQZ BYTE Low to Output Hi-Z tFHQV BYTE High to Output Valid
Max Max Max
5 25 30
5 25 30
ns ns ns
1. Sampled only, not 100% tested.
46/78
M29W128FH, M29W128FL Figure 11. Write AC waveforms, Write Enable Controlled
tAVAV A0-A22/ A-1 VALID tWLAX tAVWL E tELWL G tGHWL W tWLWH tWHEH
DC and AC parameters
tWHGL
tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 VALID tWHDX
VCC tVCHEL RB tWHRL
AI08972
Table 22.
Symbol
Write AC characteristics, Write Enable Controlled
Alt Parameter M29W128FH, M29W128FL 60 70 70 0 45 45 0 0 30 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tWHRL
(1)
tWC tCS tWP tDS tDH tCH tWPH tAS tAH
Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low
Min Min Min Min Min Min Min Min Min Min Min Max Min
60 0 45 45 0 0 30 0 45 0 0 30 50
tOEH tBUSY tVCS
Write Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Chip Enable Low
tVCHEL
1. Sampled only, not 100% tested.
47/78
DC and AC parameters Figure 12. Write AC waveforms, Chip Enable Controlled
tAVAV A0-A22/ A-1 VALID tELAX tAVEL W tWLEL G tGHEL E tELEH
M29W128FH, M29W128FL
tEHWH
tEHGL
tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 VALID tEHDX
VCC tVCHWL RB tEHRL
AI08973
Table 23.
Symbol
Write AC characteristics, Chip Enable Controlled
Alt Parameter M29W128FH, M29W128FL 60 70 70 0 45 45 0 0 30 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tEHGL tEHRL
(1)
tWC tWS tCP tDS tDH tWH tCPH tAS tAH
Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low
Min Min Min Min Min Min Min Min Min Min Min Max Min
60 0 45 45 0 0 30 0 45 0 0 30 50
tOEH tBUSY tVCS
Chip Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Write Enable Low
tVCHWL
1. Sampled only, not 100% tested.
48/78
M29W128FH, M29W128FL
DC and AC parameters
Figure 13. Reset/Block Temporary Unprotect AC waveforms (No Program/Erase ongoing)
RB
E, G tPHEL, tPHGL RP tPLPX
AI11300b
Figure 14. Reset/Block Temporary Unprotect during Program/Erase operation AC waveforms
tPLYH RB tRHEL, tRHGL E, G
RP tPLPX
AI11301b
Table 24.
Symbol
Reset/Block Temporary Unprotect AC characteristics
Alt Parameter M29W128FH, M29W128FL 60 70 20 500 50 20 0 s ns ns ns ns Unit
tPLYH(1) tPLPX tPHEL, tPHGL(1)
tREADY tRP tRH tRPD
RP Low to Read mode, during Program or Erase RP Pulse Width RP High to Write Enable Low, Chip Enable Low, Output Enable Low RP Low to Standby Mode. RB High to Write Enable Low, Chip Enable Low, Output Enable Low
Max Min Min Min Min
tRHEL tRHGL(1)
tRB
1. Sampled only, not 100% tested.
49/78
DC and AC parameters Figure 15. Accelerated Program Timing waveforms
M29W128FH, M29W128FL
VPP VPP/WP VIL or VIH tVHVPP
tVHVPP
AI05563
50/78
M29W128FH, M29W128FL
Package mechanical
9
Package mechanical
Figure 16. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20mm, package outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-b
A1
L
1. Drawing is not to scale.
Table 25.
TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20mm, package mechanical data
millimeters inches Max 1.200 0.100 1.000 0.220 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.100 20.000 18.400 0.500 14.000 0.600 3 56 19.800 18.300 - 13.900 0.500 0 20.200 18.500 - 14.100 0.700 5 0.7874 0.7244 0.0197 0.5512 0.0236 3 56 0.7795 0.7205 - 0.5472 0.0197 0 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0039 0.7953 0.7283 - 0.5551 0.0276 5
Symbol Typ A A1 A2 B C CP D D1 e E L Min
N
51/78
Package mechanical
M29W128FH, M29W128FL
Figure 17. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline
D FD FE D1 SD
E
E1
SE
ddd BALL "A1"
A
e
b A1
A2
BGA-Z23
1. Drawing is not to scale.
Table 26.
TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data
millimeters inches Max 1.200 0.300 0.800 0.350 10.000 7.000 9.900 - 0.500 10.100 - 0.100 1.000 13.000 7.000 1.500 3.000 0.500 0.500 - 12.900 - - - - - - 13.100 - - - - - 0.0394 0.5118 0.2756 0.0591 0.1181 0.0197 0.0197 - 0.5079 - - - - - 0.3937 0.2756 0.200 0.350 0.0118 0.0315 0.0138 0.3898 - 0.0197 0.3976 - 0.0039 - 0.5157 - - - - - 0.0079 Typ Min Max 0.0472 0.0138
Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD SE Min
52/78
M29W128FH, M29W128FL
Part numbering
10
Part numbering
Table 27.
Example:
Ordering information scheme
M29W128FH 70 N 6 F
Device type M29
Operating voltage W = VCC = 2.7 to 3.6V
Device function 128FH = 128 Mbit (x8/x16), Page, Uniform Block, Flash Memory, Highest Block Protected by VPP/WP 128FL = 128 Mbit (x8/x16), Page, Uniform Block, Flash Memory, Lowest Block Protected by VPP/WP
Speed 60 = 60ns 70 = 70ns
Package N = TSOP56: 14 x 20 mm ZA = TBGA64: 10 x13mm, 1mm pitch
Temperature range 6 = -40 to 85 C
Option E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel Packing
Note:
This product is also available with the Extended Memory Block factory locked. For further details and ordering information contact your nearest Numonyx sales office.
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office.
53/78
Block addresses and Read/Modify Protection Groups
M29W128FH, M29W128FL
Appendix A
Block addresses and Read/Modify Protection Groups
Table 28.
Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Block Addresses and Protection Groups
Size (KBytes/KWords) 64/32 64/32 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 1A0000h-1AFFFFh 1B0000h-1BFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh Protection Block Group Protection Group Protection Group Protection Group Protection Group (x8) 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh (x16) 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh
54/78
M29W128FH, M29W128FL Table 28.
Block 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
Block addresses and Read/Modify Protection Groups
Block Addresses and Protection Groups (continued)
Size (KBytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 3A0000h-3AFFFFh 3B0000h-3BFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh Protection Block Group (x8) 1C0000h-1CFFFFh 1D0000h-1DFFFFh (x16) 0E0000h-0E7FFFh 0E8000h-0EFFFFh
55/78
Block addresses and Read/Modify Protection Groups Table 28.
Block 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91
M29W128FH, M29W128FL
Block Addresses and Protection Groups (continued)
Size (KBytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 5A0000h-5AFFFFh 5B0000h-5BFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh Protection Block Group (x8) 3C0000h-3CFFFFh 3D0000h-3DFFFFh (x16) 1E0000h-1E7FFFh 1E8000h-1EFFFFh
56/78
M29W128FH, M29W128FL Table 28.
Block 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
Block addresses and Read/Modify Protection Groups
Block Addresses and Protection Groups (continued)
Size (KBytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 7A0000h-7AFFFFh 7B0000h-7BFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh Protection Block Group (x8) 5C0000h-5CFFFFh 5D0000h-5DFFFFh (x16) 2E0000h-2E7FFFh 2E8000h-2EFFFFh
57/78
Block addresses and Read/Modify Protection Groups Table 28.
Block 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155
M29W128FH, M29W128FL
Block Addresses and Protection Groups (continued)
Size (KBytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 9A0000h-9AFFFFh 9B0000h-9BFFFFh 4D0000h-4D7FFFh 4D8000h-4DFFFFh 960000h-96FFFFh 970000h-97FFFFh 980000h-98FFFFh 990000h-99FFFFh 4B0000h-4B7FFFh 4B8000h-4BFFFFh 4C0000h-4C7FFFh 4C8000h-4CFFFFh 920000h-92FFFFh 930000h-93FFFFh 940000h-94FFFFh 950000h-95FFFFh 490000h-497FFFh 498000h-49FFFFh 4A0000h-4A7FFFh 4A8000h-4AFFFFh 8E0000h-8EFFFFh 8F0000h-8FFFFFh 900000h-90FFFFh 910000h-91FFFFh 470000h-477FFFh 478000h-47FFFFh 480000h-487FFFh 488000h-48FFFFh 8A0000h-8AFFFFh 8B0000h-8BFFFFh 8C0000h-8CFFFFh 8D0000h-8DFFFFh 450000h-457FFFh 458000h-45FFFFh 460000h-467FFFh 468000h-46FFFFh 860000h-86FFFFh 870000h-87FFFFh 880000h-88FFFFh 890000h-89FFFFh 430000h-437FFFh 438000h-43FFFFh 440000h-447FFFh 448000h-44FFFFh 820000h-82FFFFh 830000h-83FFFFh 840000h-84FFFFh 850000h-85FFFFh 410000h-417FFFh 418000h-41FFFFh 420000h-427FFFh 428000h-42FFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh 800000h-80FFFFh 810000h-81FFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh 400000h-407FFFh 408000h-40FFFFh Protection Block Group (x8) 7C0000h-7CFFFFh 7D0000h-7DFFFFh (x16) 3E0000h-3E7FFFh 3E8000h-3EFFFFh
58/78
M29W128FH, M29W128FL Table 28.
Block 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187
Block addresses and Read/Modify Protection Groups
Block Addresses and Protection Groups (continued)
Size (KBytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 BA0000h-BAFFFFh BB0000h-BBFFFFh 5D0000h-5D7FFFh 5D8000h-5DFFFFh B60000h-B6FFFFh B70000h-B7FFFFh B80000h-B8FFFFh B90000h-B9FFFFh 5B0000h-5B7FFFh 5B8000h-5BFFFFh 5C0000h-5C7FFFh 5C8000h-5CFFFFh B20000h-B2FFFFh B30000h-B3FFFFh B40000h-B4FFFFh B50000h-B5FFFFh 590000h-597FFFh 598000h-59FFFFh 5A0000h-5A7FFFh 5A8000h-5AFFFFh AE0000h-AEFFFFh AF0000h-AFFFFFh B00000h-B0FFFFh B10000h-B1FFFFh 570000h-577FFFh 578000h-57FFFFh 580000h-587FFFh 588000h-58FFFFh AA0000h-AAFFFFh AB0000h-ABFFFFh AC0000h-ACFFFFh AD0000h-ADFFFFh 550000h-557FFFh 558000h-55FFFFh 560000h-567FFFh 568000h-56FFFFh A60000h-A6FFFFh A70000h-A7FFFFh A80000h-A8FFFFh A90000h-A9FFFFh 530000h-537FFFh 538000h-53FFFFh 540000h-547FFFh 548000h-54FFFFh A20000h-A2FFFFh A30000h-A3FFFFh A40000h-A4FFFFh A50000h-A5FFFFh 510000h-517FFFh 518000h-51FFFFh 520000h-527FFFh 528000h-52FFFFh 9E0000h-9EFFFFh 9F0000h-9FFFFFh A00000h-A0FFFFh A10000h-A1FFFFh 4F0000h-4F7FFFh 4F8000h-4FFFFFh 500000h-507FFFh 508000h-50FFFFh Protection Block Group (x8) 9C0000h-9CFFFFh 9D0000h-9DFFFFh (x16) 4E0000h-4E7FFFh 4E8000h-4EFFFFh
59/78
Block addresses and Read/Modify Protection Groups Table 28.
Block 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219
M29W128FH, M29W128FL
Block Addresses and Protection Groups (continued)
Size (KBytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 DA0000h-DAFFFFh DB0000h-DBFFFFh 6D0000h-6D7FFFh 6D8000h-6DFFFFh D60000h-D6FFFFh D70000h-D7FFFFh D80000h-D8FFFFh D90000h-D9FFFFh 6B0000h-6B7FFFh 6B8000h-6BFFFFh 6C0000h-6C7FFFh 6C8000h-6CFFFFh D20000h-D2FFFFh D30000h-D3FFFFh D40000h-D4FFFFh D50000h-D5FFFFh 690000h-697FFFh 698000h-69FFFFh 6A0000h-6A7FFFh 6A8000h-6AFFFFh CE0000h-CEFFFFh CF0000h-CFFFFFh D00000h-D0FFFFh D10000h-D1FFFFh 670000h-677FFFh 678000h-67FFFFh 680000h-687FFFh 688000h-68FFFFh CA0000h-CAFFFFh CB0000h-CBFFFFh CC0000h-CCFFFFh CD0000h-CDFFFFh 650000h-657FFFh 658000h-65FFFFh 660000h-667FFFh 668000h-66FFFFh C60000h-C6FFFFh C70000h-C7FFFFh C80000h-C8FFFFh C90000h-C9FFFFh 630000h-637FFFh 638000h-63FFFFh 640000h-647FFFh 648000h-64FFFFh C20000h-C2FFFFh C30000h-C3FFFFh C40000h-C4FFFFh C50000h-C5FFFFh 610000h-617FFFh 618000h-61FFFFh 620000h-627FFFh 628000h-62FFFFh BE0000h-BEFFFFh BF0000h-BFFFFFh C00000h-C0FFFFh C10000h-C1FFFFh 5F0000h-5F7FFFh 5F8000h-5FFFFFh 600000h-607FFFh 608000h-60FFFFh Protection Block Group (x8) BC0000h-BCFFFFh BD0000h-BDFFFFh (x16) 5E0000h-5E7FFFh 5E8000h-5EFFFFh
60/78
M29W128FH, M29W128FL Table 28.
Block 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253
Block addresses and Read/Modify Protection Groups
Block Addresses and Protection Groups (continued)
Size (KBytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group Protection Group FA0000h-FAFFFFh FB0000h-FBFFFFh FC0000h-FCFFFFh FD0000h-FDFFFFh 7D0000h-7D7FFFh 7D8000h-7DFFFFh 7E0000h-7E7FFFh 7E8000h-7EFFFFh F60000h-F6FFFFh F70000h-F7FFFFh F80000h-F8FFFFh F90000h-F9FFFFh 7B0000h-7B7FFFh 7B8000h-7BFFFFh 7C0000h-7C7FFFh 7C8000h-7CFFFFh F20000h-F2FFFFh F30000h-F3FFFFh F40000h-F4FFFFh F50000h-F5FFFFh 790000h-797FFFh 798000h-79FFFFh 7A0000h-7A7FFFh 7A8000h-7AFFFFh EE0000h-EEFFFFh EF0000h-EFFFFFh F00000h-F0FFFFh F10000h-F1FFFFh 770000h-777FFFh 778000h-77FFFFh 780000h-787FFFh 788000h-78FFFFh EA0000h-EAFFFFh EB0000h-EBFFFFh EC0000h-ECFFFFh ED0000h-EDFFFFh 750000h-757FFFh 758000h-75FFFFh 760000h-767FFFh 768000h-76FFFFh E60000h-E6FFFFh E70000h-E7FFFFh E80000h-E8FFFFh E90000h-E9FFFFh 730000h-737FFFh 738000h-73FFFFh 740000h-747FFFh 748000h-74FFFFh E20000h-E2FFFFh E30000h-E3FFFFh E40000h-E4FFFFh E50000h-E5FFFFh 710000h-717FFFh 718000h-71FFFFh 720000h-727FFFh 728000h-72FFFFh DE0000h-DEFFFFh DF0000h-DFFFFFh E00000h-E0FFFFh E10000h-E1FFFFh 6F0000h-6F7FFFh 6F8000h-6FFFFFh 700000h-707FFFh 708000h-70FFFFh Protection Block Group (x8) DC0000h-DCFFFFh DD0000h-DDFFFFh (x16) 6E0000h-6E7FFFh 6E8000h-6EFFFFh
61/78
Block addresses and Read/Modify Protection Groups Table 28.
Block 254 255
M29W128FH, M29W128FL
Block Addresses and Protection Groups (continued)
Size (KBytes/KWords) 64/32 64/32 Protection Block Group Protection Group Protection Group (x8) FE0000h-FEFFFFh FF0000h-FFFFFFh (x16) 7F0000h-7F7FFFh 7F8000h-7FFFFFh
62/78
M29W128FH, M29W128FL
Common Flash Interface (CFI)
Appendix B
Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query command is issued, the memory enters Read CFI Query mode and read operations output the CFI data. Table 29, Table 30, Table 31, Table 32, Table 33 and Table 34 show the addresses (A-1, A0-A10) used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 34: Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Table 29.
Address Sub-section Name x16 10h 1Bh 27h 40h 61h x8 20h 36h 4Eh 80h C2h CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Security Code Area Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) 64 bit unique device number Description
Query Structure Overview(1)
1. Query data are always presented on the lowest order data outputs.
Table 30.
Address
CFI Query Identification String(1)
Data Description Value "Q" Query Unique ASCII String "QRY" "R" "Y" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 33) AMD Compatible P = 40h
x16 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah
x8 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h Address for Alternate Algorithm extended Query table 0000h NA Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
63/78
Common Flash Interface (CFI) Table 31. CFI Query System Interface Information(1)
Data x16 x8 Description
M29W128FH, M29W128FL
Address Value
1Bh
36h
0027h
VCC Logic Supply Minimum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100mV VCC Logic Supply Maximum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100mV VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100mV VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 10mV Typical timeout per single Byte/Word program = 2n s Typical timeout for minimum size write buffer program = Typical timeout per individual block erase = 2n ms Typical timeout for full Chip Erase = 2n ms 2n 2n times typical times typical 2n s
3.0V
1Ch
38h
0036h
3.6V
1Dh
3Ah
00B5h
11.5V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch
00C5h 0004h 0000h 0009h 0000h 0005h 0000h 0004h 0000h
12.5V 16s NA 512ms NA 512s NA 8s NA
Maximum timeout for Byte/Word program =
Maximum timeout for write buffer program =
Maximum timeout per individual block erase = 2n times typical Maximum timeout for Chip Erase = 2n times typical
1. The values given in the above table are valid for both packages.
Table 32.
Device Geometry Definition
Data Description Device Size = 2n in number of Bytes Flash Device Interface Code description Maximum number of Bytes in Multiple-Byte program or Page= 2n Number of Erase Block Regions. It specifies the number of regions containing contiguous Erase Blocks of the same size. Erase Block Region 1 Information Number of Erase Blocks of identical size = 00FFh+1 Erase Block Region 1 Information Block size in Region 1 = 0100h * 256 Byte Value 16 MBytes x8, x16 Async. 64 1 256 64 KBytes
Address x16 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h x8 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 0018h 0002h 0000h 0006h 0000h 0001h 00FFh 0000h 0000h 0001h
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M29W128FH, M29W128FL Table 32. Device Geometry Definition (continued)
Data x16 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch x8 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Description
Common Flash Interface (CFI)
Address Value
Erase Block Region 2 Information
0
Erase Block Region 3 information
0
Erase Block Region 4 information
0
Table 33.
Primary Algorithm-Specific Extended Query Table (1)
Data Description Value "P" Primary Algorithm extended Query table unique ASCII string "PRI" "R" "I" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (bits 1 to 0) 00 = required, 01= not required Silicon Revision Number (bits 7 to 2) Erase Suspend 00 = not supported, 01 = Read only, 02 = Read and Write Block Protection 00 = not supported, x = number of sectors in per group Temporary Block Unprotect 00 = not supported, 01 = supported Block Protect /Unprotect 06 = M29W128FH/M29W128FL Simultaneous Operations: Not Supported Burst Mode, 00 = not supported, 01 = supported Page Mode, 00 = not supported, 02 = 8-Word page VPP Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100mV "1" "3" Yes
Address x16 40h 41h 42h 43h 44h 45h x8 80h 82h 84h 86h 88h 8Ah 0050h 0052h 0049h 0031h 0033h 000Ch
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh
8Ch 8Eh 90h 92h 94h 96h 98h 9Ah
0002h 0001h 0001h 0006h 0000h 0000h 0002h 00B5h
2 1 Yes 6 NA No 02 11.5V
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Common Flash Interface (CFI) Table 33.
M29W128FH, M29W128FL
Primary Algorithm-Specific Extended Query Table (continued)(1)
Data Description VPP Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100mV Value
Address x16 x8
4Eh
9Ch
00C5h
12.5V Uniform + VPP/WP Protecting Highest or Lowest Block Yes
4Fh
9Eh
0000h
Top/Bottom Boot Block Flag 00h = Uniform device
50h
A0h
0001h
Program Suspend, 00 = not supported, 01 = supported
1. The values given in the above table are valid for both packages.
Table 34.
Security Code Area
Data Description
Address x16 61h 62h 63h 64h x8 C3h, C2h C5h, C4h C7h, C6h C9h, C8h XXXX XXXX 64 bit: unique device number XXXX XXXX
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M29W128FH, M29W128FL
Extended Memory Block
Appendix C
Extended Memory Block
The M29W128F has an extra block, the Extended Memory Block, that can be accessed using a dedicated command. This Extended Memory Block is 128 Words in x16 mode and 256 Bytes in x8 mode. It is used as a security block (to provide a permanent security identification number) or to store additional information. The Extended Memory Block is either Factory Locked or Customer Lockable, its status is indicated by bit DQ7. This bit is permanently set to either `1' or `0' at the factory and cannot be changed. When set to `1', it indicates that the device is factory locked and the Extended Memory Block is protected. When set to `0', it indicates that the device is customer lockable and the Extended Memory Block is unprotected. Bit DQ7 being permanently locked to either `1' or `0' is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. Bit DQ7 is the most significant bit in the Extended Memory Block Verify Indicator and a specific procedure must be followed to read it. See Verify Extended Memory Block Protection Indicator in Table 4: Block Protection, 8-bit mode and Table 7: Block Protection, 16-bit mode, for details of how to read bit DQ7. The Extended Memory Block can only be accessed when the device is in Extended Memory Block mode. For details of how the Extended Block mode is entered and exited, refer to the Section 5.3.1: Enter Extended Memory Block command and Section 5.3.2: Exit Extended Block command, and to Table 13 and Table 9.
C.1
Factory Locked Extended Memory Block
In devices where the Extended Memory Block is factory locked, the Security Identification Number is written to the Extended Memory Block address space (see Table 35: Extended Memory Block Address and Data) in the factory. The DQ7 bit is set to `1' and the Extended Memory Block cannot be unprotected.
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Extended Memory Block
M29W128FH, M29W128FL
C.2
Customer Lockable Extended Memory Block
A device where the Extended Memory Block is customer lockable is delivered with the DQ7 bit set to `0' and the Extended Memory Block unprotected. It is up to the customer to program and protect the Extended Memory Block but care must be taken because the protection of the Extended Memory Block is not reversible. There are two ways of protecting the Extended Memory Block:
Issue the Enter Extended Block command to place the device in Extended Block mode, then use the In-System Technique with RP either at VIH or at VID (refer to Appendix D: High Voltage Block Protection, and to the corresponding flowcharts, Figure 20 and Figure 21, for a detailed explanation of the technique). Issue the Enter Extended Block command to place the device in Extended Block mode, then use the Programmer Technique (refer to Appendix D: High Voltage Block Protection, and to the corresponding flowcharts, Figure 18 and Figure 19, for a detailed explanation of the technique).
Once the Extended Memory Block is programmed and protected, the Exit Extended Block command must be issued to exit the Extended Memory Block mode and return the device to Read mode. Table 35. Extended Memory Block Address and Data
Address(1) x8 000000h-0000FFh x16 000000h-00007Fh Factory Locked Security Identification Number Data Customer Lockable Determined by Customer
1. See Table 28: Block Addresses and Protection Groups.
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M29W128FH, M29W128FL
High Voltage Block Protection
Appendix D
High Voltage Block Protection
The High Voltage Block Protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to Appendix A: Block addresses and Read/Modify Protection Groups, and Table 28 for details of the Protection Groups. Once protected, Program and Erase operations within the protected group fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. To protect the Extended Memory Block issue the Enter Extended Block command and then use either the Programmer or In-System technique. Once protected issue the Exit Extended Block command to return to read mode. The Extended Memory Block protection is irreversible, once protected the protection cannot be undone.
D.1
Programmer technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a group of blocks follow the flowchart in Figure 18: Programmer equipment Group Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 19: Programmer equipment Chip Unprotect flowchart. Table 36: Programmer technique Bus operations, 8-bit or 16-bit mode, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
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High Voltage Block Protection
M29W128FH, M29W128FL
D.2
In-System technique
The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP (1) . This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in Figure 20: In-System equipment Group Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 21: In-System equipment Chip Unprotect flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
Note:
RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Memory Block.
Programmer technique Bus operations, 8-bit or 16-bit mode
E G W Address Inputs A0-A22 A9 = VID, A12-A22 Block Address Others = X A6 = VIH, A9 = VID, A12 = VIH, A15 = VIH Others = X A0, A2, A3, A6 = VIL, A1 = VIH A9 = VID, A12-A22= Block Address Others = X A0, A2, A3 = VIL A1, A6 = VIH A9 = VID, A12-A22 = Block Address Others = X Data Inputs/Outputs DQ15A-1, DQ14-DQ0 X X Pass = xx01h Retry = xx00h.
Table 36.
Operation Block (Group) Protect(1) Chip Unprotect Block (Group) Protect Verify
VIL VID
VID VID
VIL Pulse VIL Pulse
VIL
VIL
VIH
Block (Group) Unprotect Verify
VIL
VIL
VIH
Pass = xx00h Retry = xx01h.
1. Block Protection Groups are shown in Appendix D, Table 28.
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M29W128FH, M29W128FL
Flowcharts
Appendix E
Flowcharts
Figure 18. Programmer equipment Group Protect flowchart
START ADDRESS = GROUP ADDRESS Set-up
W = VIH
n=0
G, A9 = VID, E = VIL Wait 4s
W = VIL Protect
Wait 100s
W = VIH
E, G = VIH, A1 = VIH A0, A2 to A7 = VIL
E = VIL
Wait 4s Verify
G = VIL Wait 60ns
Read DATA
DATA = 01h YES A9 = VIH E, G = VIH End PASS
NO
++n = 25 YES A9 = VIH E, G = VIH FAIL
NO
AI07756b
1. Block Protection Groups are shown in Appendix D: High Voltage Block Protection, Table 28.
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Flowcharts Figure 19. Programmer equipment Chip Unprotect flowchart
START PROTECT ALL GROUPS n=0 CURRENT GROUP = 0
M29W128FH, M29W128FL
Set-up
A6, A12, A15 = VIH(1) E, G, A9 = VID Wait 4s
Unprotect
W = VIL Wait 10ms
W = VIH
E, G = VIH
ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3, A4, A5, A7 = VIL A1, A6 = VIH E = VIL Wait 4s INCREMENT CURRENT GROUP G = VIL Verify Wait 60ns Read DATA
NO
DATA = 00h
YES
NO
++n = 1000 YES
LAST GROUP YES A9 = VIH E, G = VIH PASS
NO
End
A9 = VIH E, G = VIH FAIL
AI07757b
1. Block Protection Groups are shown in Appendix D: High Voltage Block Protection, Table 28.
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M29W128FH, M29W128FL Figure 20. In-System equipment Group Protect flowchart
Flowcharts
START Set-up
n=0
RP = VID WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Wait 100s WRITE 40h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Verify Wait 4s READ DATA ADDRESS = GROUP ADDRESS A1 = VIH, A0, A2 to A7 = VIL NO
Protect
DATA = 01h YES RP = VIH End
++n = 25 YES RP = VIH
NO
ISSUE READ/RESET COMMAND PASS
ISSUE READ/RESET COMMAND FAIL
AI07758b
1. Block Protection Groups are shown in Appendix D: High Voltage Block Protection, Table 28. 2. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Memory Block.
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Flowcharts Figure 21. In-System equipment Chip Unprotect flowchart
START PROTECT ALL GROUPS n=0 CURRENT GROUP = 0
M29W128FH, M29W128FL
Set-up
RP = VID WRITE 60h ANY ADDRESS WITH A1 = VIH, A0, A2 to A7 = VIL
Unprotect
WRITE 60h ANY ADDRESS WITH A0, A2, A3, A4, A5, A7 = VIL A1, A6 = VIH Wait 10ms
WRITE 40h ADDRESS = CURRENT GROUP ADDRESS A1 = VIH, A0, A2 to A7 = VIL Verify Wait 4s READ DATA ADDRESS = CURRENT GROUP ADDRESS A1 = VIH, A0, A2 to A7 = VIL NO YES INCREMENT CURRENT GROUP
DATA = 00h
NO End
++n = 1000 YES RP = VIH
LAST GROUP YES RP = VIH
NO
ISSUE READ/RESET COMMAND FAIL
ISSUE READ/RESET COMMAND PASS
AI07759d
1. Block Protection Groups are shown in Appendix D: High Voltage Block Protection, Table 28.
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M29W128FH, M29W128FL Figure 22. Write to Buffer and Program flowchart and Pseudo Code
Start Write to Buffer F0h Command, Block Address Write n(1), Block Address
Flowcharts
First Part of the Write to Buffer and Program Command
Write Buffer Data, Start Address
X=n
X=0 NO Abort Write to Buffer NO
YES
YES
Write to a Different Block Address
Write Next Data,(3) Program Address Pair
Write to Buffer and Program Aborted(2)
X = X-1 Program Buffer to Flash Block Address
Read Status Register (DQ1, DQ5, DQ7) at Last Loaded Address
YES DQ7 = Data NO DQ1 = 1 YES NO NO
DQ5 = 1 YES
Check Status Register (DQ5, DQ7) at Last Loaded Address
DQ7 = Data
(4)
YES
NO FAIL OR ABORT(5) END
AI08968b
1. n+1 is the number of addresses to be programmed.
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Flowcharts
M29W128FH, M29W128FL
2. A Write to Buffer and Program Abort and Reset must be issued to return the device in Read mode. 3. When the block address is specified, any address in the selected block address space is acceptable. However when loading Write Buffer address with data, all addresses must fall within the selected Write Buffer page. 4. DQ7 must be checked since DQ5 and DQ7 may change simultaneously. 5. If this flowchart location is reached because DQ5='1', then the Write to Buffer and Program command failed. If this flowchart location is reached because DQ1='1', then the Write to Buffer and Program command aborted. In both cases, the appropriate reset command must be issued to return the device in Read mode: a Reset command if the operation failed, a Write to Buffer and Program Abort and Reset command if the operation aborted. 6. See Table 9 and Table 10, for details on Write to Buffer and Program command sequence.
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M29W128FH, M29W128FL
Revision history
Revision history
Table 37.
Date 29-Sep-2005
Document revision history
Version 0.1 First Issue. Document status changed to "Full Datasheet". Title updated. Program Suspend Latency time updated in Table 15: Program, Erase Times and Program, Erase Endurance cycles. DQ7 changed to DQ7 for Program, Program During Erase Suspend and Program Error in Table 16: Status register bits. Changes
02-Dec-2005
1
07-Mar-2006
2
13-Mar-2006
3
Section 5.2.1: Write to Buffer and Program command, and Section 5.2.2: Write to Buffer and Program Confirm command updated to cover 8-bit mode. Note 2, Note 3, and Note 4 updated in Table 11: Fast Program commands, 8-bit mode.
Verify Extended Memory Block Protection bit command removed.
06-Apr-2006 25-Oct-2006 06-Nov-2006 10-Dec-2007
4 5 6 7
Table 16: Status register bits updated.
DQ7 was replaced by DQ7 for `Write to Buffer and Program Abort' in Table 16: Status register bits. Applied Numonyx branding.
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M29W128FH, M29W128FL
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